1. Technical Field
This disclosure relates to integrated circuit design, and more particularly to a method for manipulating and repartitioning a hierarchical design.
2. Description of the Related Art
Integrated circuit design flow is a complex process. Most often, a functional/behavioral description of the system/circuit is created with use of a register transfer language (RTL) or hardware description language (HDL) such as Verilog or VHDL (Very high speed integrated circuits Hardware Description Language). An important part of the design process is the creation of a logic implementation, and subsequently a transistor level implementation of these behavioral models. The creation of these implementations is oftentimes automated through the use of “synthesis” tools. Generally, a synthesis program is used to generate a netlist from the HDL models, making use of standard cell libraries containing a variety of circuit elements from which the integrated circuit may be constructed. Netlists usually include instances of the standard cells contained in the design, with the possible inclusion of custom blocks, and information descriptive of the connectivity between all the instances included in the integrated circuit. There are different types of netlists that can be used, including physical and logical netlists, instance-based and net-based netlists, and flat and hierarchical netlists. Typically, the final netlist generated by the synthesis tool is dependent on the constructs that appear in the HDL model. In other words, the style and syntax of various functional elements in the HDL oftentimes determines the type of elements and components that appear in the netlist generated by the synthesis tool.
Because the design cycle for integrated circuits is complex and there are many steps, integrated circuits may oftentimes include circuit blocks that are exchanged between designers and design engineers as completed blocks. Part of this process includes one group of engineers, e.g. working for Intellectual Property (IP) vendors, delivering RTL code representative of a given design to another group of engineers. The RTL code can include various different logic/circuit blocks residing at different levels of hierarchy. Oftentimes, such third party IP may not be partitioned in a way that is ideal for physical implementation. In such cases, the RTL design hierarchy needs to be manipulated and/or repartitioned for better physical partitioning, in which case the various wrappers representing hierarchical partitions around the completed circuit blocks may also need to be modified. In order to achieve this, the RTL is typically recoded by hand, which is a very labor-intensive operation that needs to be performed every time a major code revision is received. In addition, the coding may need to be modified, as physical partitioning is refined. The existing electronic design automation tools such as design/synthesis tools do not perform repartitioning very well, particularly in a hierarchical design, in which various circuit blocks reside at different levels of hierarchy.